This invention relates generally to dynamic random access memory (DRAM) cell devices and particularly relates to a minimization-feasible word line structure for such devices and a method of manufacturing the same.
Continued growth in the capacity of dynamic random access memory (DRAM) technology can be enhanced by minimizing the size of individual DRAM cells. Such minimization has been hampered in prior devices and methods for a number of reasons. It has been difficult to fabricate prior devices with straight word lines; it has been difficult to maintain isolation when the DRAM cell size is reduced in cases where the bit line contact (BLCT) and storage node contact (SNCT) are not formed by a process which self-aligns them to the word lines; and it has been difficult to straighten both the active region and the bit lines at the same time in the cell over bit line (COB) type of cell.
In prior devices and methods, two typical structures have generally been employed in forming word lines for DRAM cells. In the first of these, the BLCT and the SNCT are not formed by a self-aligned process to the word lines. Such prior art structures are depicted in FIGS. 1-4. With reference to FIG. 1, a first prior art structure, designated generally as 10, includes a plurality of substantially straight word lines 12 and a plurality of bit lines 14 orthogonal to the word lines 12. The structure also includes a plurality of storage node contacts 16, bit line contacts 18, and active regions 20. A cross section through structure 10 is depicted in FIG. 2. FIG. 2 shows the relationship of the word lines 12, bit lines 14, SNCTs 16 and BLCTs 18 to an insulator 22 and a LOCOS 24. In viewing FIG. 2, it will be appreciated that the word lines 12 are not self-aligned to either the SNCTs 16 or the BLCTs 18.
Still with reference to prior art structure 10, the channel length Lg of the transfer gate must be long enough in order to obtain a sufficient threshold voltage Vt. Furthermore, sufficient space is required between the word lines 12, BLCTs 18 and SNCTs 16 so that they do not touch each other. In order to meet these requirements, the length of a unit cell in the cross section perpendicular to the word lines had to become fairly large, thus impeding effective minimization of the structure. In an effort to overcome these problems, an alternative prior art structure, designated generally as 26, was developed. Reference should now be had to FIGS. 3 and 4. As shown in FIGS. 3 and 4, the width of word lines 28 was widened at the transfer gate portion in order to meet the aforementioned requirements; conversely, the remainder of the word lines were narrowed since there was no need for greater width in those regions. This resulted in an irregular shape for the word lines 28 taken in plan view as shown in FIG. 3 and in turn caused large deformations of the actual word line patterns as compared to the mask patterns in the photolithography process. In turn, difficulty was encountered in keeping the width of the word lines 28 constant at the transfer gate portion, thus resulting in a large variation of the threshold voltage Vt for the transfer gates. Further, since it was difficult to control the width of the word lines 28 due to the irregular shape, it was not practical to reduce cell size of the unit cell since the minimum stepper resolution could not be taken advantage of, as is the case for straight word lines.
Note that the remainder of the items depicted in FIG. 3, including the bit lines 14, storage node contacts 16, bit line contacts 18 and active regions 20 have all received the same numbering as in FIGS. 1 and 2.
FIGS. 9 and 10 depict another alternative to the prior art structure, which is designated generally as 30. Word lines 12, SNCTs 16, active regions 20, insulator 22 and LOCOS isolators 24 have received the same numbering as in FIG. 1. Alternative structure 30 includes bit lines 32 and BLCTs 34. It will be appreciated that in prior art structure 30, a portion of the footprint of the BLCT 34 is placed over the isolation region. This can result in degradation of isolation performance between adjacent active regions or leakage from the BLCT 34. The cause was etching off of a portion of the isolation region in the process of etching the hole for the BLCT 34. It will be appreciated that similar problems would be encountered if modification was made to locate part of the SNCT footprint over the isolation region.
FIG. 11 depicts yet another prior art alternative to the structure 10 of FIG. 1, designated generally as 36. The word lines 12, SNCTs 16 and active regions 20 have received the same numbering as in FIG. 1. Bit lines 38 are formed in a completely straight configuration, which is desirable. The BLCTs 40 cross over both the active region and the isolation region, in order to connect to the straight bit lines 38, as depicted for the cell over bit line (COB) configuration of FIG. 11. In theory, the configuration of FIG. 11 can enable minimization of the length of the unit cell in the cross section parallel to the word lines 12. However, in practice, similar problems w ere encountered to those discussed above for the configuration of FIGS. 9 and 10.
Reference should now be had to FIGS. 5 and 6 which depict a prior art structure, designated generally as 42, wherein the BLCTs 44 and SNCTs 46 are formed by a self-aligned process to the word lines 48.
Structure 42 also includes bit lines 50, LOCOS isolation structure 52, and first and second insulators 54, 56 respectively. It will be appreciated that the structure 42 permits use of straight word lines 48 and permits the word lines 48 to be self-aligned to the SNCT 46 and BLCT 44. Unfortunately, the BLCTs 44 and SNCTs 46, although they are self-aligned to the word lines 48, are not self-aligned to the active region. Furthermore, the structure 42 exhibits many of the deficiencies discussed above for the structure 10.
Prior art structures have generally employed two types of isolation. These are the LOCOS isolation method as depicted in FIG. 7 and the trench isolation method as depicted in FIG. 8. As depicted in FIG. 7, in the LOCOS method, a plurality of LOCOS isolators 58 are embedded in the surface 60 of a substrate 62 and extend both inwardly and outwardly therefrom, with the active region 64 formed in between the LOCOS isolators 58.
Reference should now be had to FIG. 8, which depicts a trench isolation structure. A plurality of trench insulators 66 are formed in a substrate 70 are flush with the surface 68 thereof. Active regions 72 are formed between trench insulators 66.
The prior-art trench isolation method depicted in FIG. 8 is prone to a problem with the characteristic of the source to drain current versus the gate voltage. Reference should now be had to FIGS. 12A and 12B, wherein the same reference characters as employed in FIG. 8 are used. Also depicted are word line 74, gate insulator 76 and corner regions 78. A corner region 78 of the active region is formed at the boundary between the active region and the isolation region at trench insulator 66. This occurs when the upper edge of the trench insulator 66 is located below the surface of the active region, as best seen in the detail of FIG. 12B. In this case, an enhanced electric field results in the corner region 78 due to the gate being surrounded by the corner-shaped region. This in turn results in a xe2x80x9ckinkxe2x80x9d on the order of double the threshold voltage Vt in the characteristic source to drain current versus gate voltage. This was due to localized lowering of the threshold voltage Vt in the corner region 78.
Therefore, a need has arisen in the art for a word line structure for a DRAM cell which will permit effective minimization of the DRAM cell size with straight word lines, effective isolation via self-alignment of the BLCTs and SNCTs to the active region, and with straight active regions and straight bit lines as well. There is also a need for a method of manufacturing such a DRAM word line structure. The present invention provides a word line structure for a DRAM, and a method of manufacturing the same, which substantially reduce or eliminate the aforementioned problems with prior devices and techniques.
In accordance with the present invention, a word line structure for a DRAM cell comprises a generally planar substrate; a plurality of mesa-shaped active regions; a plurality of substantially straight and parallel word lines; and an insulation layer. The plurality of mesa-shaped active regions are formed on the generally planar substrate and protrude outwardly a given distance from the substrate. The active regions have outer surfaces at the given distance from the substrate and each of the outer surfaces has two word-line-receiving regions formed in it. Each of the word-line-receiving regions has a floor portion.
The plurality of substantially straight and parallel word lines each have inner and outer surfaces. Two of the plurality of word lines are embedded in the two word-line-receiving regions formed in the outer surfaces of the mesa-shaped active regions. The inner surfaces of the word lines are located inwardly of the outer surfaces of the mesa-shaped active regions and are adjacent to the floor portions.
The insulation layer is positioned on the substrate and has an insulation layer thickness. The insulation layer forms a plurality of isolation regions between the plurality of mesa-shaped active regions. The isolation regions have outer edges located outwardly from the floor portion of the word-line-receiving regions formed in the outer surfaces of the mesa-shaped active regions at boundary locations. A given boundary is formed by a given one of the mesa-shaped active regions, a given one of the isolation regions, and a given one of the word lines.
More specifically, in one embodiment of the present invention, the insulation layer thickness is such that the insulation layer generally terminates in a main outer surface which is located just inward of the outer surface of the mesa-shaped active regions. In this embodiment, the word line structure further comprises a layer of gate oxide material located between the word lines and the word-line-receiving regions. The gate oxide material is in communication with the insulation layer. Further, the word line structure also further comprises a plurality of finger portions which are integral with the insulation layer and extend outwardly from it. These finger portions enclose the word lines and define a plurality of Si3N4-receiving cavities therebetween. Finally, in this embodiment, a layer of Si3N4 is located in the Si3N4-receiving cavities. The Si3N4 material is employed because it is an insulator which can be selectively etched with respect to SiO2.
In another embodiment of the present invention, the insulation layer thickness is such that the insulation layer generally terminates in a main outer surface which is located outward of the outer surfaces of the mesa-shaped active regions. The word lines are formed with inner doped polysilicon portions having inner surfaces and outer low resistance portions with outer surfaces. The inner doped polysilicon portions extend outwardly to a level even with the main outer surface of the insulation layer and the insulation layer is formed with a plurality of outwardly extending fingers which extend outward beyond the main outer surface of the insulation layer. The outwardly extending fingers are located between the word lines and form Si3N4-receiving cavities therebetween. The word line structure of the second embodiment further comprises a layer of gate oxide material located between the word lines and the word-line-receiving regions, with the gate oxide material in communication with the insulation layer, and a layer of Si3N4 located in the Si3N4-receiving cavities and surrounding the outer low-resistance portions of the word lines.
In accordance with the present invention, a method of manufacturing a word line structure for a DRAM cell comprises the steps of forming a generally planar substrate; forming a first plurality of Si3N4 fingers, with a plurality of void regions therebetween; extending the depth of the void regions to form word-line-receiving regions; and placing a plurality of word lines into the word-line-receiving regions. In the step of forming the generally planar substrate, the substrate is formed with a plurality of mesa-shaped active regions protruding outwardly a given distance therefrom. The active regions have outer surfaces at the given distance from the substrate, and the substrate has a layer of insulation formed over it which extends over both the substrate and the active regions. The insulation forms a plurality of isolation regions between the plurality of active regions. The isolation regions have outer edges.
In the step of forming the plurality of Si3N4 fingers, the fingers are formed on the layer of insulation and extend outwardly from the layer of insulation. The fingers define a plurality of void regions between the fingers and the void regions have a depth which extends inwardly to the layer of insulation.
The step of extending the depth of the void regions includes extending the depth of those regions to form word-line-receiving regions, such that those of the void regions located over the active regions extend into the active regions to form the word-line-receiving regions therein and such that those of the void regions not located over the active regions extend into the layer of insulation to form the word-line-receiving regions therein. The word-line-receiving regions have floor portions and the floor portions of those of the word-line-receiving regions in the mesa-shaped active regions are located inwardly of the outer edge of the isolation regions.
More specifically, in a first method, the step of placing the plurality of word lines can include the sub-steps of applying doped polysilicon into the word-line-receiving regions and then applying a layer of low resistance material over the doped polysilicon. The method can comprise the additional steps of applying a layer of insulation over the low resistance material in the void regions; and removing the Si3N4 fingers such that the layer of insulation forms a plurality of insulation fingers which extend outwardly and have a width co-extensive with the low resistance material. The insulation fingers define a plurality of interstices therebetween. The method can further comprise the steps of adding additional insulation to enhance the width of the insulation fingers; removing insulation material at inward portions of the interstices to expose the outer surfaces of the active regions where the interstices are adjacent the active regions, and to extend the interstices inward of the outer surfaces of the active regions where the interstices are adjacent the isolation regions. A further step can include filling the interstices with Si3N4. This method can be used, for example, to manufacture a structure according to the first embodiment discussed above.
In an alternative method, the step of placing the plurality of word lines into the word-line-receiving regions can include the sub-steps of applying doped polysilicon into the word-line-receiving regions and applying a layer of low resistance material over the doped polysilicon for each of the word-line-receiving regions. The layer of low resistance material for each of the word-line-receiving regions can have a width greater than that of its corresponding word-line-receiving region, but sufficiently narrow so as not to touch an adjacent one of the layers of low resistance material. The method can further comprise the additional steps of removing the first plurality of Si3N4 fingers and then forming a second plurality of Si3N4 fingers which surround the layers of low resistance material. The second plurality of Si3N4 fingers terminate at the layer of insulation and in turn form a plurality of insulation-receiving gaps therebetween. Finally, the method can include the step of filling the plurality of insulation-receiving gaps with insulation.
Technical advantages of the present invention include maintenance of an adequate transfer gate length Lg even with narrow word lines; maintaining isolation between the BLCTs, SNCTs and word lines; minimization of unit cell size; and elimination of undesirable xe2x80x9ckinksxe2x80x9d in the characteristic source-to-drain current versus gate voltage. Further, the present invention can be formed with a low-resolution stepper with reduced manufacturing steps, thus resulting in reduced manufacturing costs.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.